The 3D-Flow Architecture Breakthrough: A Universal, Scalable Digital Processor for Real-Time Pattern Recognition in High-Rate Data Streams — A Platform to Save Millions of Lives and Billions of Euros
The 3D-Flow Architecture Breakthrough: A Universal, Scalable Digital Processor for Real-Time Pattern Recognition in High-Rate Data Streams — A Platform to Save Millions of Lives and Billions of Euros
A Revolutionary ATCA/VME/VXI 3D-Flow Board: 512 Channels, >2,800 Programmable Operations—Scalable to >50,000 Operations on Each Dataset Arriving Every 25 ns with Zero Data Loss at a fraction of the cost of FPGA
DALLAS, Dec. 20, 2025 (GLOBE NEWSWIRE) — In PDF https://bit.ly/437YX7H) The Crosetto Foundation for the Reduction of Cancer Deaths, a registered nonprofit organization, urgently calls on the public to help expose and correct scientific and institutional inconsistencies that any person—with or without a scientific background—can understand through common sense and factual evidence.
A Media Snippet accompanying this announcement is available by clicking on this link.
These inconsistencies have harmed taxpayers, patients, and the advancement of science. They can be fixed with dialogue, transparency, and your support. Please consider contributing $10, $20, $50, or whatever you can via online donation (https://crosettofoundation.org/donate-now/) or if you have Zelle app on your phone/computer, send your donation directly to donate@crosettofoundation.org [1]. If you cannot donate, your voice still matters—read on to learn how to take action by writing to your Member of the Parliament.
Notice to Readers:
The full version of this 60-page scientific article, including complete references, factual data, and detailed calculations, is available in PDF format at: https://bit.ly/437YX7H
Due to platform limits on document length, this abridged version includes the titles and subtitles of all sections, along with selected explanatory paragraphs and references listed at the end.
Only Section 16 (Thirty Years of Missed Opportunities to Fund the Non-Recurring Engineering, NRE) and Section 17 (Final Call to Action) are reproduced in full. Other sections contain only headings and specific paragraphs containing citations. Consequently, these sections may lack the necessary context for full comprehension and require to access the full document.
Readers who require additional technical detail, background explanations, or full documentation are invited to consult the complete PDF version.
This article is divided into three parts.
Part I — Scientific Evidence: The Case for Accountability and Scientific Integrity (Section 1 through 7) documents the facts, public records, and actions revealing a persistent suppression of transparency and scientific accountability that has caused tremendous financial waste and slowed progress in particle physics at CERN and in cancer detection and prevention.
Part II Technical Proofs, Industrial Comparisons, and Specifications (Sect. 8 through 15), presents the technical evidence. It demonstrates the fundamental architectural limits of FPGA-based systems in executing complex algorithms on datasets arriving at ultra-high rates without data loss, and contrasts these limitations with the 3D-Flow architecture. The 3D-Flow architecture was officially recognized in 1993 at Fermilab as a breakthrough invention capable of overcoming these barriers with unprecedented performance and cost-effectiveness, yet it has remained chronically unfunded and continually suppressed. (See the scientific article of 14/4/2025 [2], which supports the two-hour IEEE presentation of 102 slides granted to Crosetto in 2024 at the conference that accepted all six of his papers, and the Press Release in HTML and PDF of 28/8/2025 [3] which describes the missed opportunities that result in the loss of billions of taxpayer euros and millions of lives).
Part III — The Cost of Delay and the Final Imperative (Sect. 16 through 17) analyzes the real-world consequences of the three-decade funding gap, synthesizes the evidence, provides a mandate for immediate action to rescue scientific integrity and protect taxpayer investment and defines the ethical, scientific, and institutional actions required to restore accountability, prevent further waste of public resources, and enable progress that serves science and humanity
Part I: Scientific Evidence: The Case for Accountability and Scientific Integrity
The Genesis, Proven Merit, and Unjust Suppression of the 3D-Flow Architecture: A Three-Decade-Spanning Account of Technical Triumph and Institutional Failure
The speed of light is constant, but the ability of humanity to process the data it reveals is not.
Every major scientific endeavor—from the search for the smallest particles at the Large Hadron Collider (LHC) to the diagnosis of life-threatening diseases using Positron Emission Tomography (PET)—is fundamentally limited by one bottleneck: Real-Time Digital Processing. Data arrives from detectors at rates equivalent to hundreds of thousands of gigabits per second, but traditional computing architectures, reliant on centralized buses and commercial Field-Programmable Gate Arrays (FPGAs), cannot keep pace.
The insistence on these flawed conventional strategies has already cost taxpayers dearly: ignoring the proven 3D-Flow invention in favor of FPGAs has wasted over $4 billion during the past three decades at CERN.
Worse, the most recent CERN implementation of the FPGA-Based Level-1 Trigger planned for the 2026-2036 decade is a 650 kW system containing an incredibly high number of transistor, 20 trillion in all, which would waste over $12 billion [4] if this technically inadequate solution is not scrapped.
It is inadequate at filtering relevant data from 8 billion events per second from the HL-LHC costing $4 million/day to operate, wasting also the salary of thousands of scientists analyzing for several years irrelevant data.
These systems routinely discard over 99% of the raw information they receive, often including the very ‘needle in the haystack’ event scientists are seeking. Chapter 1 defines this crisis, explaining why conventional, multi-billion-dollar processing strategies are not just technically deficient but financially irresponsible when confronted with the 21st-century data deluge.
(See additional Press Releases from June through October 2025 published by over 5,000 NEWS Outlets [5] that have reached a potential of over 800 million readers [6], [7], [8], [9], [10], [11], [12], [13], [14], [15], [16], [17].
1. The Core Scientific Challenge
1.1 Challenge in Real-Time Digital Processing
The challenge of real-time data processing is fundamental to both scientific discovery and clinical diagnostics. Whether Filtering 8 billion events per second from the High-Luminosity Large Hadron Collider (HL-LHC) or processing high-rate radiation data in medical imaging for early-stage cancer detection, the need for a programmable, high-throughput, universal solution is critical.
1.2 Crosetto’s 3D-Flow Invention Solves the Core Challenge and Is Designed to Serve Scientists’ Needs
1.3 Official Recognition and Funding for 3D-Flow
Crosetto’s invention of the 3D-Flow architecture [18] in 1992 was officially recognized in 1993 by a major public scientific review at FERMILAB [19]. In 1995, the U.S. Department of Energy awarded Crosetto a $1 million grant for a feasibility study [20] (See pages 34-44 of [2]).
Figure 1. Isometric view of the 3D-Flow processor also referred as a ‘Logical Unit’ or ‘Processing Element (PE)’, illustrating the various input and output ports (top in figure). The bottom portion of the figure displays the timing diagram of five 3D-Flow pipeline stages (See Figure 24, page 37 of [2].
Figure 2. Sequence of the flow of data in different times in one 3D-Flow electronic channel (See Table V, page 37 of [2].
Figure 3. Example of algorithms executed on the 3D-Flow processor (12 to 18 operations per clock, average 13). (Page 114-116 of [25]).
1.4 Technology-Independent Development Suite
1.5 3D-Flow for Life-Saving Diagnostic Applications
This versatile architecture enables instantaneous, high-throughput processing, essential not only for Level-1 Triggering at the HL-LHC but also for real-time pattern detection for life-saving diagnostics—specifically, the ability to identify tumors at the earliest curable stage [25], [28], [29].
2. Scientific Validation and Proof of Feasibility
2.1 Peer-Reviewed Proof of Feasibility and Architectural Advantage
The positive results of the DOE-funded feasibility study, including the design of two universal analog and digital input boards, were published in a 1999 peer-reviewed 45-page article in Nuclear Instruments and Methods in Physics Research (NIM Sec. A, vol. 436, pp. 341–385). [21].
In this article, Crosetto demonstrated the 3D-Flow design’s capability to execute up to 26 operations in a single cycle (e.g., add, subtract, multiply, compare one value with 24 values, etc.) for a number of cycles longer than the 25 ns dataset-arrival interval.
2.2 Public Demonstration of the Simulation of 3D-Flow for a Complete Level-1 Trigger (2000)
In 2000, at the IEEE-NSS-MIC Conference, Crosetto provided a demonstration of the 3D-Flow simulator for thousands of processors and the application development tools. He also presented two articles [22], [23] and distributed 200 free copies of his book, ‘400+ times improved PET efficiency for lower-dose radiation, lower-cost cancer screening’ [24], detailing the 3D-Flow architecture’s advantages in medical imaging and its potential to save lives through cost-effective early cancer detection. Despite its relevance, Crosetto’s book has not been cited in 25 years, though many have copied the ideas and content Crosetto presented therein.
2.3 Hardware Proofs of 3D-Flow Functionality
2001 (First Proof): Crosetto presented a working hardware [25] proof of concept at the IEEE-NSS-MIC conference.
2003 (Scalability Proof): Crosetto demonstrated the feasibility and scalability of a 144-processor 3D-Flow system (on 36 Altera FPGAs, costing $500 per processor, operating at 20 MHz) for high-energy physics (HEP) and Medical Imaging applications, by building industrialized IBM-PC modular boards at his own expense [26]. Successful inter-board [27] communication proved that a scalable 3D-Flow system could be built for any detector size in High-Energy Physics (HEP) or Medical Imaging, ensuring all relevant information is extracted at the lowest cost per valid signal captured.
3. Fabricability and Missed Technological Opportunities
3.1 Fabricability Proof and the First Missed Opportunity (1997)
3.2 The Missed 120 nm CMOS Opportunity: Capability to Meet LHC Requirements Through 2026
Crosetto’s repeated requests to meet with the DOE to explain the advantages of 3D-Flow over non-programmable ASICs and FPGAs were consistently denied. Instead, the DOE funded a single researcher with over $50 million for a project that did not simulate the entire trigger system. This latter project subsequently attracted over $100 million from European funding agencies to implement the CMS Level-1 trigger using ASICs and FPGAs, and ultimately failed. The 4,000 boards were scrapped in 2016 due to their ineffectiveness, as reported by the system’s own designers [28].
4. Documented Limitations and Failures of FPGA-Based Triggers
4.1 Documented Failures of FPGA-Based Level-1 Triggers to Meet LHC Requirements
Public records clearly shows that for the past 25 years, CERN has repeatedly built inadequate FPGA-based Level-1 Triggers, necessitating multiple rebuilds.
During the Higgs boson discovery announcement on 4 July 2012, only 40 events were detected out of ~100,000 produced by 1,000 trillion LHC collisions over two years.
These 40 events were likely recorded by chance, demonstrating the fundamental unsuitability of FPGA architecture for Level-1 Trigger, a fact Crosetto has demonstrated (pages 46-49 of [2]).
5. Institutional Decisions and the Record of Suppression
5.1 DOE Solicitation and Continued Suppression (2015-2016)
Following the recognized failure in 2015 of the 4,000 CMS FPGA-Based Level-1 Trigger boards that were scrapped the following year as it is publicly documented [22], the Director of the High Energy Physics Office at the U.S. DOE solicited Crosetto to prepare a proposal for a universal Level-1 Trigger.
Crosetto submitted a detailed 274-page proposal [29], supported by 59 quotes from 21 reputable industries, including quotes to port the 1997 synthesis (four 3D-Flow processors/chip, 350 nm CMOS @ 61 MHz) to a more advanced 64 processors/chip, 40 nm CMOS technology @ 400 MHz (estimated cost: NRI + ~$1 per processor).
This proposal was never examined by the DOE, and a requested meeting was never granted.
… CERN has approved and already built a new FPGA version for 2026–2036—yet again relying on a design consuming 650 kW FPGA-Based CMS Level-1 Trigger system, built from 20 trillion transistors [30], [31] and demonstrably unable to meet HL-LHC real-time requirements.
5.2 High-Level Scientific Meetings and Continued Inaction (2016)
… After meeting one-on-one at the same conference with CERN Director of Research and explaining the advantages of the 3D-Flow proposal [29] Crosetto requested a public meeting be organized at CERN between himself and the designers of the CERN FPGA-Based Level-1 trigger, which was denied.
Instead, the Director used €17 million from the European H2020 ATTRACT Grant (No. 777222) to fund WPET (Wearable PET), a scientifically implausible and logistically impractical 350+ kg coat for 24-hour cancer screening [32], [33].
5.3 European Parliamentarians Intervene (2017 & 2021)
… Parliamentary Question [34] (translated into 24 languages) on the 3D-CBS project [25] (see 11 minute educational video [35]) to the European Commission, demanding transparency regarding the unjustified funding of the impractical WPET project and an explanation for the suppression of the scientifically validated 3D-CBS project (which uses 3D-Flow for early cancer detection).
2021: …Instead of investigating, the European Commission awarded another €28 million [36] to the CERN-ATTRACT consortium that funded the WPET project in 2019.
6. The Continued Suppression of Unrefuted Scientific Evidence (2024-2025)
In October 2024, all six of Crosetto’s scientific papers were approved by the seven Chairs of the IEEE-NSS-MIC-RTSD Conference. He was granted two hours to present his 102-slide presentation [37]. Despite answering all questions, supporting his presentation with an 82-page scientific article [2].
6.1 Overview: Suppression of Transparency and Failure of Scientific accountability
6.1.1. November 2024 (IEEE silencing)
Access to Crosetto’s six conference presentations was deliberately made difficult by changing the online URL, and the two-hour video of the presentations was temporarily removed without notification (see Section IX, page 28 of [2]).
6.1.2. April 2025 (TechArchiv censured)
Crosetto’s article [3] detailing the 3D-Flow architecture and its advantages compared to FPGA and other approaches was suppressed from the open platform TechArchiv without scientific justification, forcing its publication as a Press Release in order to ensure continued accessibility to the scientific community and the public.
6.1.3. May 2025 (Proven Solution Ignored)
Crosetto’s two-page technical abstracts—one summarizing the performance, power consumption, and cost comparison [38] between 3D-Flow and the CERN FPGA-Based CMS Level-1 Trigger, and the other summarizing a revolutionary, universal, scalable 3D-Flow board [39] capable of executing complex Level-2 trigger algorithms at Level-1—were ignored by CERN and suppressed by the 2025 IEEE-NSS-MIC-RTSD Conference without reason.
6.1.4. 20 June 2025: CERN $12 Billion Mistake
On 20 June 2025, the CERN Council approved [40] funding for major upgrades to the ATLAS and CMS experiments (https://bit.ly/4mDncCi), including a CMS Level-1 Trigger system based on approximately 20 trillion transistors and consuming about 650 kW of power [30], [31], as well as a similar FPGA-based system for ATLAS.
6.1.5. July 2025 (IEEE-NSS-MIC-RTSD suppression of the 3D-Flow solution without providing a feedback)
On 3 July 2025, Crosetto received an email from the IEEE-NSS Chairs stating ‘We regret to inform you that your abstracts (#2905 [38] and #2954 [39]) have not been accepted for presentation in the 2025 IEEE NSS MIC RTSD conference… If you would like detailed feedback regarding why your submission was not accepted, please respond to this message.’
Despite multiple follow-up phone calls and emails, no such feedback was ever received. Consequently, on 16 July 2025, Crosetto sent a formal letter [41] to 43 IEEE leaders and other senior figures in the field, explaining the scientific importance of the rejected work and requesting that its content be openly discussed with colleagues.
In the weeks leading up to the conference, Crosetto continued to write respectfully to these 43 leaders, reiterating his willingness to engage in technical dialogue. In parallel, he formally requested permission [42] from the conference organizers and notified Yokohama law enforcement authorities of his intention to distribute 1,200 technical documents to conference participants, in order to ensure peaceful, transparent, and lawful scientific communication.
6.1.6. 3 November 2025: Suppression of a Question at the IEEE Plenary Session
On 3 November 2025, during the first IEEE-NSS Plenary Session—attended by approximately 800 scientists in person (+ remotely connected)—the IEEE-NSS Chair moderating the session prevented Crosetto from asking a question of the keynote speaker [43].
6.1.7. 4 November 2025: IEEE-CERN: The Unanswered Questions. A $12+ Billion Waste of Taxpayer Funds
On 4 November 2025, at the IEEE-NSS Session, Crosetto pursued a path of open scientific dialogue by posing two critical, quantifiable questions directly to the CERN-ATLAS and CMS speakers regarding the performance and cost of their FPGA-Based Level-1 Trigger:
Performance: ‘Please provide the number of programmable basic operations the CERN-FPGA-Based Level-1 Trigger can perform on each dataset arriving every 25 nanoseconds without data loss’.
Cost: ‘Please provide the cost per electronic channel’.
Both speakers were unable to answer these fundamental questions. Despite a formal written follow-up sent to the CERN CMS and ATLAS collaboration leadership on 14 November 2025 [44], no response has been received.
Technical Inadequacy
Leadership Accountability
The existence of a superior alternative—the 3D-Flow processor and system architecture—has been known since its formal recognition as a breakthrough in 1993. Key ATLAS and CMS leaders (currently member of the CMS Management and Executive Board) were directly involved in this process (see details at [44]).
The IEEE Presentation Controversy: A Question of Impartiality
A serious question of impartiality surrounds the IEEE-NSS Chairs’ Decision:
According to the official list of IEEE-NSS topics and submission at [45], a total of 592 papers were submitted to the 2025 Conference. Of these, only 12 papers were rejected. As shown in the conference summary graph ([46]), only three rejections occurred in the critical DAQ–Trigger category (the fifth line of topics). Notably, two of those three rejections corresponded to the 3D-Flow papers that explicitly demonstrated a viable solution
Figure 4. Slide presented on 7 November 2025 at the IEEE-NSS Closing Session showing the official NSS Topics (note the fifth line: DAQ, Trigger and Front End Electronics).
Figure 5. Slide presented on 7 November 2025 at the IEEE-NSS Closing Session showing that, among 592 submitted papers, only 12 were rejected; only three rejections occurred in the DAQ Trigger category (fifth topic line), and two of those were the 3D-Flow papers demonstrating a solution to the Level-1 Trigger problem, while FPGA-Based papers that cannot meet LHC requirements were approved.
6.1.8. Escaping Accountability: Removal of the Trigger Topic from the 2026 IEEE-NSS in Madrid and its Impact on 90% of CERN’s $3 Billion Annual Budget
… IEEE-NSS-MIC-RTSD General Chair and NSS-Chair for the 2026 Conference in Madrid removed the ‘Trigger’ category from the official NSS Topics. The program now lists only ‘DAQ, front end and electronics,’ [47] as confirmed on the IEEE website: [https://nssmic.ieee.org/2026/program/].
This omission is not a minor organizational adjustment. It represents a significant evasion of scientific and financial accountability affecting 90% of CERN’s $3 Billion Annual Budget.
The Central Role of the Trigger
The Trigger is the central electronic unit upon which the relevance and effectiveness of multiple downstream components depend.
- Data Acquisition (DAQ) systems exist to capture scientifically valuable data. When the trigger fails to discriminate valuable signals from noise, DAQ systems merely record irrelevant information.
- Investments in detectors, front-end electronics, and data analysis pipelines become ineffective if the trigger does not ensure that recorded data are meaningful.
The Cost of Failure
The High-Luminosity LHC (HL-LHC) absorbs approximately 90% of CERN’s $3 billion annual budget, as detailed in Section 9.1.3 of [3]. Without an effective Level-1 Trigger capable of executing complex, long algorithms on each dataset arriving every 25 ns—resolving pileup, exchanging data with neighboring channels, and correlating information across sub-detectors—the HL-LHC cannot achieve its scientific objectives.
The Question of Scientific Integrity
What is the rationale for Eliminating ‘Trigger’ from the 2026 conference topics?
Who Must Demand Accountability?
- All European Member States and associated countries that finance CERN.
- Oversight authorities responsible for scientific integrity, ethical conduct, and financial accountability.
- Institutions committed to preventing further waste during the HL-LHC program spanning 2026–2042.
Figure 6. 2026 NSS Topics presented at the IEEE-NSS Closing Session on 7 November 2025 showing that the ‘Trigger’ topic has been removed (also available on the IEEE website: https://nssmic.ieee.org/2026/program/).
7. Public Conduct, Transparency, and Benefit to Humanity
7.1 Crosetto’s Longstanding Respect for Science, Colleagues, and Taxpayers: A Factual Record of Conduct and a Clarification of What Is Truly Disrespectful
(See more about Crosetto’s commitment to science [48]. See also public scientific review at [49].
Respectful Actions vs. Institutional Evasion
The True Disrespect: Harm to Science and Taxpayers
The more serious concern, for institutions and taxpayers, is:
- Is it respectful to science to suppress evidence instead of refuting it?
- Is it respectful to colleagues to prevent open dialogue on technical contradictions?
- Is it respectful to taxpayers to continue publicly funded programs without answering quantifiable scientific questions?
History ultimately judges not personalities, but whether scientific decisions followed evidence or avoided it.
7.2 Unwavering Public Dialogue: Yokohama (2025)
To establish a dialogue based on scientific evidence rather than authority, Crosetto took the significant step of personally distributed from 3 to 7 November 2025, 1,200 two-page flyers and carrying two large posters (1 m x 1.5 m) to the 1,789 scientists attending the IEEE-NSS-MIC-RTSD conference in Yokohama, Japan. Several participants stopped to speak with Crosetto, expressing encouragement, appreciation for his perseverance, and urging him to continue presenting documented scientific evidence.
7.2.1. Incontrovertible Scientific Evidence
7.2.2. Comprehensive Documentation and Transparency
7.2.3. Benefit to Science and Humanity
Part II: Technical Proofs, Industrial Comparisons, and Specifications
Part I established the history of suppression; Part II the technical demonstration of the limitations of FPGA executing complex algorithm on dataset received at ultra-high speed without data loss and 3D-Flow architecture officially recognized at FERMILAB in 1993, but unfunded and continue to be suppressed. To fully appreciate the magnitude of the 3D-Flow advantage, a rigorous and honest appraisal of the incumbent technology is required.
This Part II initiates that technical deep dive by analyzing the actual, field-proven performance of FPGA-based commercial digital processing boards across ten critical industries—from high-speed defense systems to industrial measurement and scientific readout.
The analysis does not just list products; it deconstructs the underlying architectural compromises that constrain these boards:
- Limited on-chip routing and I/O bottlenecks.
- High power per unit of logic.
- Significant cost per unit of processing.
These compromises render FPGAs suitable primarily for applications requiring simple, programmable combinatorial logic, limiting them to solving relatively simple equations. FPGAs are fundamentally inadequate for executing complex pattern-recognition algorithms that require thousands of basic operations while simultaneously sustaining a high input data rate with no data loss, even when parallelism is applied.
Furthermore, the inherent limitations on parallelism in FPGAs are severe, a constraint that the 3D-Flow architecture demonstrates can be vastly exceeded (exceeding 250 parallel circuit copies in the boards designed in this document) due to its superior architectural concept.
By detailing the specifications and limitations of devices from NI, Keysight, ADI, and others, this analysis establishes the current performance ceiling for general-purpose FPGA solutions, providing the necessary, quantifiable benchmark against which the revolutionary efficiency and throughput of the 3D-Flow will be measured
8. Commercial FPGA-Based Digital Processing Systems: Industry Survey
8.1 Comparative Analysis: Detailed Performance Metrics of Commercial Digital Processing Boards Based on FPGAs Across Key Industry Leaders
Following are the ten major companies and categories that manufacture or sell these types of electronic boards and systems:
Major High-Performance & Modular DAQ Manufacturers
These companies offer modular systems, many of which use standard form factors like PCIe, PXIe, or various embedded form factors, often with on-board FPGA processing:
8.1.1. National Instruments (NI / Emerson): Evaluating Scalability and Throughput in Industrial Test Systems
8.1.2. Keysight Technologies: Assessing High-Speed Data Acquisition and Real-
8.1.3. Analog Devices (ADI): Analyzing Integrated Signal Processing and Power Efficiency for Embedded Systems
8.1.4. Yokogawa Electric Corporation: Performance in High-Reliability Industrial
8.1.5. ADLINK Technology – Taiwan / Global: Examination of Performance in Edge Computing and Communication Platforms
8.1.6. UEI (United Electronic Industries) – United States: Reviewing Rugged, Real-Time Data Acquisition in Extreme Environments
8.1.7. GaGe (a Vitrek brand) – USA: Detailed Look at Ultra-High-Speed Digitizers and Signal Processing
8.1.8. Electro Standards Laboratories (ESL) – USA: The Constraints and Opportunities in Custom FPGA Board Manufacturing
8.1.9. CAEN: Performance in Nuclear and Particle Physics Readout Systems
8.1.10. XIA: Specialized Analysis in Digital Pulse Processing for Scientific Instruments
9. Algorithm Analysis: Performance Limitations of FPGA-Based Processing
Comparison between the commercial boards and the 3D-Flow boards
9.1 Real-Time Threshold / Edge / Peak Detection Pipeline (fully pipelined at ≥1 GS/s)
This is the most standard real-time sequence used in oscilloscopes, trigger systems, radar front-ends, and digitizers.
Operations performed for each sample (executed every 1 ns):
- Baseline Estimation
Bn = alpha * Bn-1 + (1 – alpha) * xn
Operations: 1 multiply + 1 subtract + 1 add (Total 3 operations)
- Real-Time FIR Filter (e.g., 7–15 taps) at 1 GS/s
FIR filtering is one of the canonical real-time FPGA algorithms.
General equation: y[n] = sum_{k = 0 to M-1} h[k] * x[n – k] (Example 7-tap FIR 7 multiply and 6 add, total 13 operations/ns
9.2 What real-time GS/s FPGA systems cannot do
They cannot (and do not attempt to):
- Execute hundreds or thousands of operations per dataset at 40 MS/s.
- Perform complex branching logic or deep computation on every sample.
- Execute CPU-style sequential algorithms.
They rely on limited pipeline parallelism only.
This is far below the thousands of operations per dataset that 3D-Flow demonstrates (Section 3).
10. Quantitative Comparison: FPGA vs 3D-Flow
10.1 The Core Architectural Challenge: Executing Complex Pattern-Recognition Algorithms at Ultra-High Data Streams Without Data Loss
To execute Level-2 Trigger algorithms—which require thousands of operations—at Level-1, on every dataset arriving every 25 ns at each electronic channel without data loss, conventional designs would need to replicate circuits many times (parallelism).
Today the Level-1 Trigger requires even more operations to cope with pile-up, to exchange data with neighboring channels, and to correlate information across sub-detectors. These tasks are impossible for an FPGA to perform on each dataset arriving every 25 ns.
In contrast, the 3D-Flow architecture can execute such algorithms and enables new capabilities that were previously unthinkable—exactly as recognized in the final report of the 1993 Fermilab scientific review. On page 6, the reviewers stated [18]:
‘…given this feature, experimenters would probably think of clever uses not now possible. Better level one triggering will reduce the data rate into level two. If a large enough reduction could be achieved, level two triggers could be replaced by a processor farm.’
This statement provides a scientifically justified basis for eliminating Level-2 triggers, because the 3D-Flow demonstrates that Level-2 algorithms can be executed at Level-1. Yet decision-makers adopted FPGAs—without demonstrating that they could execute Level-2 algorithms at 40 MHz data streams without data loss.
FPGAs are not suitable for executing complex pattern-recognition algorithms because their architecture cannot sustain long sequential computations. Conversely, CPUs, GPUs, ARM processors, or Hypercube architectures—while capable of long sequences—cannot sustain ultra-high-speed input/output data streams.
Crosetto solved both limitations with the invention of the technology-independent, scalable 3D-Flow processors and system architecture, which makes it possible to build systems with an effectively unlimited number of parallel processors, sustaining any input data rate and executing any complex algorithm.
…Doing so would be unreasonable, analogous to asking HP or Acer to equip their laptops with a 35-billion-transistor, 300-Watt, 250-MHz Xilinx Virtex Ultrascale VU19P FPGA to emulate an Intel i7 processor containing only 3 billion transistors and consuming 25 Watts at 3.9 GHz (see Table VI, page 48 of [2]).
3D-Flow provides optimal results when implemented in the most cost-effective technology, as stated in Crosetto’s 45-page peer-reviewed 1999 article [21]. On page 345 he wrote:
‘…it can be implemented at any time using the technology of the day. This in turn will allow achieving, at any moment in time, the best performance in terms of power dissipation, size, speed and, consequently, cost.’
- A 120 nm CMOS implementation of the 3D-Flow Integrated Circuit (IC) in 1999 would have met LHC requirements through 2026.
- A 20 nm CMOS implementation today will satisfy requirements through 2042 and beyond.
After verifying 3D-Flow functionality in FPGA, Crosetto made clear in the same 1999 article that a full 3D-Flow implementation in FPGA is unacceptable. Funding the NRE for the ASIC design, validated in FPGA and compiled by Synopsys in 350 nm CMOS, is long overdue.
10.2 Quantitative Comparison of Level-1 Trigger Architectures: FPGA-Based $1 Billion versus $85,500 3D-Flow for 4,096 Channels and 2,821 Operations per Dataset
10.2.1. The unacceptable Scenario: Scaling Cost and Power of an FPGA-Emulated 3D-Flow Architecture (~$1 Billion, ~10 MW)
10.2.2. The Viable Solution: Feasible Cost and Efficiency of the Optimized 20 nm CMOS 3D-Flow Architecture (~$85,500, ~3 KW)
10.2.3. Conclusions of the Quantitative Comparison of Level-1 Trigger Architectures: FPGA-Based versus 20 nm CMOS 3D-Flow
This quantitative comparison conclusively demonstrates that, while the 3D-Flow architecture is fully capable of executing thousands of operations on each dataset arriving every 25 ns without data loss, achieving such performance using FPGA technology is both technologically and economically infeasible.
In contrast, a 20 nm CMOS implementation of the 3D-Flow, achieves the required performance with vastly superior metrics:
- Two orders of magnitude fewer processors
- Four orders of magnitude lower cost
- Approximately three to four orders of magnitude lower power consumption
- Minimal volume and infrastructure requirements
This confirms the necessity of funding the Non-Recurring Engineering (NRE) required to fabricate the 3D-Flow processor in a CMOS technology (around 20 nm), where cost, power, volume, and performance are simultaneously optimized.
11. The Paradigm Shift in Real-Time Processing: Summary Table of 3D-Flow vs. Commercial Solutions
The Paradigm Shift in Real-Time Processing: A Comparative Table Detailing the Transformative Advantage of Universal, Scalable 3D-Flow Boards Over Commercial FPGA Solutions
Scientific Comparison Table (Updated With 12,000 and 50,000+ Operations)
Table I. FPGA GS/s Systems vs. 3D-Flow Real-Time Architecture
| Metric |
FPGA Systems (UltraScale/Virtex + digitizers) |
Crosetto’s 3D-Flow Architecture |
| Technology |
7 nm FINFET |
20 nm Low Power CMOS |
| Clock frequency |
200–400 MHz (routing-limited) |
620 MHz (1.6 ns cycle) |
| Power consumption |
200 W – 300 W per FPGA IC |
<5 W per 128 PEs 3D-Flow IC |
| Latency sensitivity |
Highly sensitive; deep computation impossible |
Latency irrelevant as long as throughput sustained |
| Ops per clock per unit |
1 op per DSP slice per 4–5 ns |
13 ops/cycle Avg.; 26 max |
| Ops per Level-1 Trigger dataset at full 40 MHz input rate |
<100 ops/dataset |
>12,000 ops/dataset@ 40 MHzon 128-ch ATCA board, |
| Scalability of parallelism |
Hits ‘brick wall’ due to routing; cannot scale |
Linear scalabilitydue to bypass switch |
| Fanout |
One driver → many loads (major timing bottleneck) |
Zero fanout: point-to-point bypass switch |
| Routing/transistor usage |
80–90% wasted on routing & LUT configuration |
Majority used for arithmetic + control |
| Board-level performance |
Limited pipelines; timing failure at scale |
>50,000 ops/dataset @ 40 MHz on 32-Channels ATCA board |
| Suitability for Level-1 triggers / real-time pattern recognition |
Fundamentally mismatched; cannot sustain required ops |
Purpose-built, deterministic, real-time solution, exceeds requirements |
| CERN Level-1 Trigger Systems |
CMS-FPGA-Based ~650 kW |
3D-Flow-Bases system ~6 kW |
Ultimately, it compares also the 3D-Flow boards with the latest FPGA-Based Level-1 trigger designs developed and built for the 2026–2036 HL-LHC era by the ATLAS and CMS experiments at CERN [30].
12. Defining the Future of Real-Time Systems: Comprehensive Technical Specifications of the Universal, Scalable 3D-Flow Processing Board
The 3D-Flow design is adaptable to multiple industry form factors, including PXI, PXIe, PCIe, CompactDAQ, CompactRIO, 6U VME64, ATCA, 9U VME, and VXI. This versatile architecture provides instantaneous, high-throughput capability essential for applications such as HL-LHC Level-1 Triggering and real-time detection of early-stage tumors.
12.3 Parallelism and Layer Stack Calculations
Stack Layers – these execute the real-time pattern recognition algorithm.
Pyramid layers – these reduce many channels into fewer channels and route results to a single output channel. (See the description of the 3D-Flow pyramid Channel reduction and routing results to a single exit channel on pages 117-121 of [25])
The generic calculation of the layers-stack of boards with different input channels is the following
General formula
To find the number of stack layers for any board:
(128 PEs per IC × number of ICs on the board ÷ number of input channels) − 2 pyramid layers
12.3.1. 6U-VME Board with 12 ICs
12.3.2. VXI/ATCA/9U-VME Board with 66 ICs:
12.4. Sustained Throughput Capacity Calculations
12.4.1. 6U-VME Throughput
12.4.2. VXI/ATCA/9U-VME Throughput
13. Solving the Grand Challenge in High-Energy Physics: Example Implementation of the 3D-Flow Universal Scalable ATCA/9U-VME/VXI Boards for Critical Level-1 Trigger Systems
13.1 The Comprehensive Design Layout: Integrating the Entire Level-1 Trigger System Architecture for the LHC and Future HL-LHC Experiments
Figure 7. The entire Level-1 programmable system of over 68,000 x 3D-Flow processors at $0.5 each can fit into a single crate. A patch panel PRAI-ATCA receives events from the detectors, synchronizes and formats each event into 4,096 channels datasets and send them to the 3D-Flow system —one every 25 nanoseconds. (Available in PDF at [50]).
13.2 Unmatched Density and Computing Power Sustained at Ultra-High Input Data Rates: Technical Details of the Crate, Connectors, and Cables in a 3D-Flow VXI Crate Achieving 4,096 Channels and >2,800 Operations Per Dataset Arriving Every 25 ns
Figure 8. Overview of the complete 3D-Flow-Based Level-1 Trigger system suitable for multiple experiments (Available in PDF at [51].
13.3 Detailed Design and Placement of 66 3D-Flow ICs on a VXI Board (Achieving 512 Channels, >2,800 Operations Per Dataset, Scalable to >50,000 Operations Per Dataset)
Figure 9. Front view of the component layout on a 512-channel VXI board with 66 ICs (8,448 x 3D-Flow PEs). (Available in PDF at: [52]).
Figure 10. Back view of the component layout on a 512-channel VXI board with 66 ICs (8,448 x 3D-Flow PEs). (Available in PDF at: [52]).
14. Revolutionizing Medical Imaging: Example Implementation of the 3D-Flow Universal Scalable 6U-VME Board for Extracting All Valuable Biophysiological Data from Radiation in a High-Sensitivity 3D-CBS Device
The ultra-sensitive 3D-CBS [53], [25] (3-D Complete Body Screening) technology PET/CT based on the 3D-Flow invention for particle detection is targeted to significantly reduce cancer deaths and healthcare costs and is the first true paradigm change in biomedical imaging because it offers four advantages no other device can offer simultaneously:
- an effective early detection of anomalous biological processes and diseases such as cancer at a highly curable stage, including improved diagnosis, prognosis and effective monitoring of treatments, as it is capable of detecting less than 150 Bq activity in humans;
- a radiation dose 2.5% of current PET devices,
- a 2-minute effective screening examination covering all organs of the body, and
- a very low examination cost, less expensive, and more effective that can replace mammograms, PAP tests, colonoscopies, PSA tests, and others.
It is capable of extracting ALL valuable information from radiation (spatial, time and energy resolution and sensitivity) related to biological processes at the lowest cost per valid signal captured from tumor markers.
Universal Efficacy Test
One way to maximize the reduction of cancer deaths and costs would be to demand that funding agencies using taxpayer and donation money to fight cancer, whether through a new drug, vaccine, medical imaging device, or healthy lifestyle promotion, etc., estimate the reduction of cancer deaths and cost they expect to attain with their project (or combined with other existing techniques) and present a plan to test it on a sample population similar to the ROADMAP Table at reference [54].
For example, test the plan on at least 10,000 people, ages 55-74 taken from a location where the mortality rate has been constant for the past 20 years. A difference or no difference in the mortality rate will quantify the success or failure of the proposed solution. This project plans to test 60,000 people per year and achieve a 33% reduction of cancer death in 6 years and 58% in 10 years.
14.1 Technical Details of the 3D-Flow 6U-VME Crate Configuration: PEs, Connectors and Cables for 2,304 Channels (>2,000 Ops/Dataset), Designed for Cost-Effectively Measuring Photon Energy, Time, and Resolution from Low-Cost Crystal Detectors in High-Sensitivity 3D-CBS
Figure 11. Logical and physical layout of the 3D-Flow 6U-VME Crate Configuration: PEs, Connectors and Cables for 2,304 Channels (>2,000 Ops/Dataset), Designed for Cost-Effectively Measuring Photon Energy, Time, and Resolution from Low-Cost Crystal Detectors in High-Sensitivity 3D-CBS (Available in PDF at: [55]).
…the Foundation urgently calls on the public to support the request to Texas Secretary of State, the Honorable Jane Nelson, to organize a public meeting [8] between the inventor, Italian-American scientist Dario Crosetto, and CPRIT scientists, who are managing $6 billion of public funds that Nelson appropriated to eradicate cancer and of which $3.65 billion has already been spent.
This is where the parallel with High-Energy Physics is crucial.
The heart of early cancer detection lies in the ability to capture and interpret all useful signals from radiation, efficiently and accurately.
14.2 Design and Placement of 12 3D-Flow ICs on a Single 6U-VME Board (Achieving 128 Channels, >2,000 Ops/Dataset, Scalable to >9,000 Ops/Dataset)
Figure 12. Component layout on a 128-channel 6U-VME board with 12 ICs (1,536 x 3D-Flow PEs). (Available in PDF at: [56]).
15. Economic and Performance Advantage of 3D-Flow Board and Crate Configurations
Table II. 3D-Flow Board and Crate Configurations: Performance, Channels, and Cost per Channel
| Feature |
6U VME64 Board |
ATCA / 9U VME Board |
| |
|
|
| 3D-Flow ICs (PEs) |
12 ICs (1,536 PEs) |
66 ICs (8,448 PEs) |
| Power Dissipation |
60 W |
330 W |
| Cost (Single Board) |
$2,000 |
$7,000 |
| |
|
|
|
Performance &Cost |
Number of Programmable Operations on Each Dataset Arriving Every25 nsat Each Channel, with Zero Data Loss |
Number of Programmable Operations on Each Dataset Arriving Every25 nsat Each Channel, with Zero Data Loss |
| Board Configuration: |
# Channels / # Operations /
Cost per Channel |
# Channels / # Operations /
Cost per Channel |
| Option 1 (Highest Chs. Density) |
128 ch / 2,015 ops /$15 |
512 ch / 2,821 ops /$13 |
| Option 2 (Medium Chs.Density) |
64 ch / 4,433 ops /$31 |
256 ch / 6,045 ops /$27 |
| Option 3 (High Performance) |
32 ch / 9,269 ops /$62 |
128 ch / 12,493 ops /$54 |
| Option 4 (Very High Performance) |
(N/A) |
64 ch / 25,389 ops /$109 |
| Option 5 (Ultra High Performance) |
(N/A) |
32 ch / 51,181 ops /$218 |
| |
|
|
| Crate Configuration |
16-Board 6U VME64 Crate |
8-Board ATCA/9U Crate |
| Total PEs / Cost |
25,344 PEs /$47,500 |
68,352 PEs /$85,500 |
| |
|
|
| Option 1 (Max # Channels / Minimum # Operations) |
(N/A) |
4,096 ch / 2,821 ops |
| Option 2 (Medium # Channels / Medium # Operations) |
2,048 ch / 2,015 ops
|
2,048 ch / 6,045 ops
|
| Option 3 (Standard # Channels / High # Operations) |
1,024 ch / 4,433 ops
|
1,024 ch / 12,493 ops
|
| Option 4 (Low # Channels / High # Operations) |
512 ch / 9,269 ops |
512 ch / 25,389 ops
|
| Option 5 (Very Low # Channels / Very High # Operations) |
(N/A) |
256 ch / 51,181 ops |
Part III The Cost of Delay and the Final Imperative
16. Thirty Years of Missed Funding Opportunities
16.1 Comprehensive Timeline of Missed Opportunities and Funding Failures (NRE)
Timeline of Missed Funding for the 3D-Flow Integrated Circuit
Summary of Missed Funding and Decision Failures
The six critical missed funding opportunities are summarized below
16.1.1. 1997 — The Foundational RejectionDOE Failure to Fund the First Tape-Out of a Fabricable 350 nm CMOS IC (4 PE/IC, 61 MHz)
Context: Architecture Validation and Synthesis
The 3D-Flow processor and system architecture were rigorously validated prior to CMOS synthesis. Validation encompassed the simulation of the entire Level-1 Trigger processing chain, from raw detector input datasets to the final single-channel trigger decision.
Each input dataset consists of a packet of bits originating from the fast detectors. This packet contains data fields with various meanings and widths assigned by different experiments, such as 12-bit ADC values, 4-bit tracking data, 2-bit pad information, 8-bit time stamps, and other experiment-specific data. The 3D-Flow processors exchange this data with immediate neighbors in programmable array sizes (e.g., 3×3, 4×4, up to 7×7), enabling localized, real-time computation.
Each experiment (e.g., ATLAS, CMS) applies its own programmable Level-1 Trigger equations to this locally exchanged data, reflecting distinct physics goals and particle-search strategies. This capability—customized local processing with deterministic neighbor communication—makes the 3D-Flow architecture a universal platform capable of serving diverse and evolving high-energy physics experiments.
System-Level Simulation
The complete 3D-Flow architecture was validated using a full system-level C++ simulator covering the entire trigger path.
VHDL-Level Simulation
The 3D-Flow processor design was independently simulated at the VHDL level using tools from three FPGA vendors (ORCA, Altera, and Xilinx), ensuring functional correctness and vendor independence.
Following these validations, the design—integrating four processing elements (PEs) per IC—was successfully synthesized by Synopsys in 350 nm CMOS technology. The resulting IC was specified to operate at 61 MHz, and complete tape-out files were generated for fabrication at the TSMC silicon foundry.
Missed Funding
Although the U.S. DOE had previously funded Crosetto the $1 million feasibility study, it did not provide the NRE required to pay the foundry for fabrication. This funding gap prevented tape-out and blocked essential hardware validation of an already synthesized and validated IC.
16.1.2. 1999 — Ignoring Future Requirements: Missed Opportunity for a 120 nm CMOS IC Capable of Meeting LHC Requirements Through 2026 (4 PE/IC, 120 MHz)
Context
By porting the validated 3D-Flow design to 120 nm CMOS technology, integrating 16 PEs per IC and operating at 120 MHz, the resulting system could have met the LHC event-processing requirement of approximately 1.2 billion events per second through 2026.
Missed Funding
This opportunity was not funded. Instead, the DOE allocated more than $50 million to a single researcher whose work did not include full end-to-end trigger-system simulation. That project later attracted over $100 million from European funding agencies to implement CMS Level-1 Trigger systems based on ASICs and FPGAs—systems that ultimately failed.
16.1.3. 2001 — Hardware Proof Dismissed: Ignored Functional Demonstration of an 8-Processor 3D-Flow System (2 Altera FPGAs, 4 PE/FPGA, 20 MHz, $500/PE)
Context
Crosetto demonstrated a fully functional hardware implementation of the 3D-Flow architecture using two large Altera FPGAs (four processors per FPGA) operating at 20 MHz. This proof-of-concept was publicly demonstrated at an IEEE conference booth.
Missed Funding
Despite this physical, operational validation, no NRE funding was provided to complete the final ASIC implementation.
16.1.4. The Ignored Path to Scalability: Dismissal of a 144-Processor Modular System Scalable to Detectors of Any Size (36 Altera FPGAs, 4 PE/FPGA, 20 MHz, $500/PE)
Context
Crosetto personally funded and built a 144-processor 3D-Flow system using 36 Altera FPGAs mounted on two industrial-grade modular boards. This system conclusively demonstrated scalability for both high-energy physics detectors and medical imaging applications.
Missed Funding
This successful, self-funded demonstration of scalability and feasibility in hardware was ignored by funding agencies.
16.1.5. Repeating History: Failure to Fund a 40 nm CMOS IC Despite Scrapping the FPGA Trigger (64 PE/IC, 400 MHz, ~$1/PE)
Context
After the failure and scrapping of the CMS FPGA-based trigger, the U.S. DOE Director of High-Energy Physics—Crosetto’s former supervisor at the SSC—requested a new proposal. Crosetto submitted a detailed, 274-page proposal [29 supported by 59 quotes from reputable industries, including two independent cost quotations for porting the design from 350 nm to 40 nm CMOS (64 PEs per IC, NRE plus approximately $1 per processor).
Missed Funding
The proposal was never examined, the NRE was not funded, and resources were instead directed to yet another FPGA-based design—the current system incorporating approximately 20 trillion transistors and dissipating ~650 kW—which simulations indicate will also fail.
16.1.6. The Current Urgent Imperative: Final Opportunity to Fund the Cost-Optimized 20 nm CMOS IC (128 PE/IC, 620 MHz, ~$0.50/PE)
Context
The current 3D-Flow design is ready for porting to 20 nm CMOS technology, integrating 128 processing elements per IC. This implementation would enable execution of more than 50,000 programmable operations per dataset arriving every 25 ns, with zero data loss—meeting HL-LHC requirements through 2042 and beyond.
Missed Funding / Current Request
This represents the final and urgent opportunity to fund the NRE required to fabricate the validated 3D-Flow IC and capitalize on more than three decades of proven development, before another decade of scientific opportunity and public resources is lost.
17. Final Call to Action: Demanding Accountability, Public Demonstration, and Immediate Funding for the 3D-Flow Technology
17.1 Ending the Three-Decade Inconsistency: A Mandate to Stop the Pattern of Suppression and Fiscal Waste
The detailed timeline of the missed opportunities to fund the NRE for the fabrication of the 3D-Flow Integrated Circuit presented in Section 16 is not merely a record of unfortunate events. It documents a three-decade pattern of systemic inconsistency and decision failures that has actively suppressed a transformative technology from receiving the Non-Recurring Engineering (NRE) funding required for fabrication and experimental validation on a full Level-1 Trigger system and 3D-CBS for a cost-effective early cancer detection.
The consequence is measurable and staggering: billions in taxpayer funds have been committed to more expensive, less scalable, and repeatedly inadequate solutions—most notably the FPGA-based Level-1 Trigger—while a proven, cost-optimized alternative was repeatedly excluded from transparent, quantitative comparison.
This section therefore serves as a mandate to immediately cease this pattern of scientific malpractice.
Continuing to deny funding for the final, cost-optimized $0.50/PE 3D-Flow IC after decades of documented failures and escalating costs is no longer a defensible technical judgment. It is an act of gross fiscal negligence.
Funding agencies and political bodies must require an immediate end to bureaucratic and institutional roadblocks that have consistently prioritized internal, less efficient approaches over demonstrably superior innovation. The time for deliberation has passed. The time for action—to halt systemic waste and restore scientific accountability—is now.
17.2 Demand for Public Transparency: Two Measurable Questions Journalists Must Ask CERN Leadership to Stop Taxpayers Waste of $2.63 Million per Day Since 2010—and $4 Million per Day Under the New HL-LHC
Taxpayers, parliamentarians, and the public deserve direct answers to two precise, measurable, non-political questions that CERN leadership has consistently avoided for decades—questions that go to the heart of performance, cost, and accountability. These answers are essential to halt the massive waste of taxpayer funds, which currently amounts to $2.63 million per operational day for the LHC and will reach $4 million per operational day for the new HL-LHC.
Question 1 — Performance
How many programmable basic operations can CERN’s FPGA-based Level-1 Trigger execute on each dataset arriving every 25 nanoseconds, without data loss?
Question 2 — Cost
What is the cost per electronic channel of the CERN FPGA-based Level-1 Trigger?
This responsibility does not rest with CERN alone. Journalists, parliamentarians, and public administrators who act as stewards of taxpayer money have a duty to compel clear, documented answers to these two questions. When public institutions manage multi-billion-euro scientific infrastructures, transparency on performance and cost is not optional; it is a prerequisite for democratic accountability.
On 4 November 2025, during an IEEE-NSS session in Yokohama attended by 1,789 scientists, Italian-American scientist Dario Crosetto posed these two quantitative questions directly to the CERN ATLAS and CMS speakers responsible for the Level-1 Trigger systems. Neither speaker was able to provide an answer.
Despite a formal written follow-up sent on 14 November 2025 to CERN CMS and ATLAS leadership [44], no response has been received.
Rather than addressing these legitimate questions of public accountability—and rather than comparing their systems with Crosetto’s proven 3D-Flow capability, which executes 2,000 to more than 50,000 operations on each dataset arriving every 25 ns at a cost of $13 to $218 per electronic channel—CERN instead diverted public attention with a misleading promotional announcement.
In its 9 December 2025 statement, CERN reported that:
‘Over the full lifetime of the LHC, the ATLAS and CMS have now each been delivered an integrated luminosity of 500 fb⁻¹, equating to approximately 50 million billion particle collisions.’ [57].
This figure is scientifically irrelevant to the core issue. The relevant scientific questions are:
- How many meaningful physics signatures were produced?
- How many of those signatures were actually detected by the Level-1 Trigger?
When thousands of operations per dataset are required to identify subtle or rare particles at input rates of 1.2 billion events per second at the LHC—and 8 billion events per second at the HL-LHC—a system capable of executing only a few dozen operations on each dataset arriving every 25 nanoseconds—makes substantial, mathematically unavoidable data loss a certainty.
This situation is analogous to:
- An emergency room with too few doctors for critical patients; even perfect triage cannot prevent deaths when capacity is insufficient.
- A fruit harvest with too few workers; most of the crop rots because it cannot be collected in time.
In both cases, failure is caused not by poor organization, but by quantitative inadequacy of processing capacity.
Were the Level-1 Trigger capable of executing thousands of programmable operations per dataset using Crosetto’s 3D-Flow architecture, a significantly larger fraction of relevant events would be captured. Instead, multiple FPGA-based trigger implementations at CERN were built over decades, dismissed due to ineffectiveness, and then rebuilt again with the same technology.
This cycle of failure culminated in 2010–2011, when only 40 Higgs boson events were recorded—most likely by chance—out of 100,000 expected from 1,000 trillion proton-proton collisions over two years.
The economic consequences are staggering:
- Past waste: More than $4 billion already spent due to inefficient triggering, with daily expenditures running at $2.63 million per LHC operational day.
- Future waste: More than $12 billion projected to be wasted over the next decade, with daily expenditures reaching $4 million per LHC operational day.
This is no longer a theoretical debate.
It is a matter of measurable performance, documented cost, and public accountability.
Silence is no longer acceptable
17.3 Mandate for a Public Scientific Review: Parliamentarians and Funding Agencies Must Require CERN to Organize a Public Technical Comparison Between CERN’s FPGA-Based Level-1 Trigger Team and Crosetto’s 3D-Flow Architecture
Closed-door decisions can no longer be justified after thirty years. To restore confidence in scientific governance, institutional integrity, and fiscal responsibility, parliamentarians, public administrators responsible for public funds, and directors of funding agencies (e.g., the U.S. Department of Energy and the CERN Council) must issue a formal mandate requiring CERN to organize a live, public scientific and technical review of this matter.
A clear precedent exists. In 1993, the Director of the Superconducting Super Collider—who was also Director of Fermilab, then home to the most powerful particle accelerator in the world—called for a major public scientific review of Crosetto’s 3D-Flow invention [19]. That review was successfully completed, and the technology was formally recognized as a breakthrough enabling the execution of complex Level-2 trigger algorithms at Level-1.
With the same rigor and transparency, funding authorities must now require a public meeting featuring direct, head-to-head presentations and technical interrogation of the following two teams:
- The CERN FPGA-Based Level-1 Trigger Development Team
- Crosetto, presenting the 3D-Flow Level-1 Trigger Architecture
The review must focus on quantified, verifiable metrics directly relevant to HL-LHC requirements, including:
- Computational performance per dataset arriving every 25 ns, without data loss
- Ability to serve multiple experiments and other applications with a universal architecture
- Cost per electronic channel
- Demonstrated scalability and power efficiency
This is the only scientifically valid and ethically defensible method to determine which technology best serves global science and taxpayers.
Complete public documentation of the review—including presentations, numerical comparisons, technical questions, and final conclusions—must be disclosed without restriction. Such a review is not a request; it is an obligation of institutions funded by taxpayers. No credible scientific reason exists to oppose a transparent, collegial, data-driven evaluation. Any refusal to participate, or refusal to provide quantified answers, would itself constitute evidence of systemic avoidance and failure of accountability.
Extension to Medical Applications: Public Review of 3D-Flow in 3D-CBS for Early Disease Detection
The same public-review procedure should be applied to the medical applications of Crosetto’s 3D-Flow invention, specifically its use in 3D-CBS (3-D Complete Body Screening) for detecting minimal abnormal biophysiology, including early cancer markers. These abnormalities can precede clinically manifest disease and, when detected early, are associated with substantially higher survival probabilities.
As a former Texas State Senator, the Honorable Jane Nelson played a key role in allocating $6 billion in public funds through the Cancer Prevention and Research Institute of Texas (CPRIT) to fight cancer. Now, as Texas Secretary of State, she is in a unique position to safeguard transparency, accountability, and measurable outcomes for both taxpayers and patients.
Her commitment to this mission is evident in her own public statements, including a video in which she emphasizes the obligation to ensure that public investment in cancer research produces measurable results [58] (see: https://www.youtube.com/watch?v=v7VJhz7easo).
Secretary Nelson has been aware of Crosetto’s early-cancer-detection invention for more than twenty-five years. It is therefore in the best interest not only of fulfilling her mission, but of serving the public interest, to require the organization of a public scientific comparison between:
- Crosetto, presenting the 3D-CBS system based on 3D-Flow, and
- CPRIT-funded scientists and any alternative techniques or devices claimed to offer a more cost-effective solution to detect tumor markers with a lifesaving potential.
This comparison must be conducted openly and rigorously, given that CPRIT manages $6 billion in public funds, of which $3.65 billion has already been spent, originally appropriated to eradicate cancer.
If there are valid reasons to deny taxpayers access to the benefits of the 3D-CBS invention—projected to save more than 260 premature cancer deaths per device per year—then taxpayers deserve to hear those reasons in a transparent, public, evidence-based discussion.
The unrefuted calculation of 260 lives saved per device per year is presented on page 6 of [54]. This calculation is supported by well-established clinical survival statistics for cancers detected at an early, curable stage, including:
- 98% survival for breast and prostate cancer
- 91% for colon cancer
- 50% for lung cancer
17.4 The Path Forward: Crosetto Must Be Immediately Funded the Non-Recurring-Engineering (NRE) to Port the Technology-Independent 350 nm CMOS 4-PE IC to the Cost-Optimized 20 nm CMOS, 128 PE/IC
The path to resolving this decades-long contradiction is straightforward, rapid, and cost-effective.
Crosetto must be immediately funded to complete the Non-Recurring Engineering (NRE) required to port the proven, technology-independent 350 nm CMOS 3D-Flow IC (4 PE/IC) to a cost-optimized 20 nm CMOS implementation integrating 128 processing elements per IC operating at 620 MHz.
This single action would:
- Provide the first physical demonstration of a universally programmable Level-1 Trigger processor capable of executing complex Level-2 algorithms directly at Level-1.
- Reduce power consumption from hundreds of kilowatts to a few kilowatts while sustaining full real-time processing without data loss.
- Prevent more than €12 billion in projected taxpayer waste by replacing the current CERN FPGA-based Level-1 Trigger system—comprising approximately 20 trillion transistors and dissipating ~650 kW—which has repeatedly failed and been rebuilt at public expense, with a scalable, technology-independent 6 kW 3D-Flow architecture capable of meeting the requirements of all LHC experiments through 2042 and beyond.
- Increase scientific efficiency by enabling more advanced data-selection algorithms earlier in the processing chain, thereby reducing the number of days the accelerator must operate at costs of several million euros per day.
- Deliver a unified, scalable hardware platform applicable both to high-energy physics and to early cancer detection through medical imaging.
- Send a clear signal to the scientific community that transparency, innovation, and integrity have been restored to publicly funded decision-making.
The cost of this NRE is negligible compared with the scale of public funds it would protect. A single, informed decision can halt thirty years of recurring waste.
Proven Ability to Deliver with Exceptionally Low Execution Risk
From a taxpayer’s perspective, execution risk matters more than promises.
Crosetto’s record demonstrates an unusually low risk profile for the proposed NRE. He has repeatedly designed, built, and validated complex electronic systems that functioned correctly at first implementation, often under severe resource constraints.
A clear example dates to 1989 at CERN, where Crosetto designed and built a highly compact, state-of-the-art electronic board (FDPP [59]), whose component density left virtually no margin for additional components. After fabrication, he invited a visiting student from Turin, Stefano Buono, to generate software-based test signals. Working shoulder by shoulder in the same office-laboratory environment, they successfully tested the board without external assistance or redesign, relying solely on logical analysis and internal corrections of PAL (Programmable Array Logic).
Crosetto later demonstrated the same capability by independently designing and building a modular 3D-Flow board in FPGA [27], which independent reviewers estimated would normally require a full engineering team and several hundred thousand dollars to develop.
That same student, Stefano Buono, later founded a company that he sold fifteen years later for $3.9 billion. The relevance of this episode is not personal recognition, but risk assessment: it illustrates Crosetto’s proven ability to deliver functioning, high-complexity hardware under real-world conditions.
This pattern—design, build, test, and verify—has consistently characterized Crosetto’s work. His methodology relies on experimental validation and measurable results, not assumptions.
Accordingly, funding the NRE is not a gamble. It is a prudent, final engineering step with a clearly bounded cost, exceptionally low execution risk—already demonstrated by a 144-processor 3D-Flow system [27] built using 36 Altera FPGAs—and the potential to eliminate massive ongoing waste while delivering long-term scientific and medical benefits for taxpayers.
17.5 Protecting Scientific Integrity and Taxpayer Investment: Crosetto’s Ethical Mandate—Disclosure of Technical Drawings, Patent Protection, a Free License to CERN, and an Open Call for Collegial Endorsement Based on Scientific Integrity and Ethics to Secure Funding for the Benefit of Humanity
Crosetto is guided by a vision of science governed by rules, ethics, transparency, and mutual recognition among researchers, in which all stakeholders respect the rule of law to advance knowledge and contribute to the collective well-being of society.
To accelerate scientific progress and ensure that innovation delivers public benefit—not only in high-energy physics (HEP), but also in medical imaging and many other fields—Crosetto has taken the following actions:
- Patent Protection
Crosetto has filed patents covering his inventions, including the universal, cost-effective, scalable, and configurable 3D-Flow board. This step is intended to encourage industrial investment and to protect the investment of companies willing to manufacture the technology at scale, thereby accelerating the delivery of its benefits to the public.
Scientific Responsibility, Public Accountability, and the Ethical Obligation to Act
This document has presented a detailed, evidence-based account of more than thirty years of missed opportunities, during which demonstrably inefficient technological choices at CERN resulted in the waste of approximately $4 billion in public funds, with an additional $12 billion projected over the coming decade if the recently deployed CERN FPGA-based Level-1 Triggers—incapable of meeting LHC requirements—are not reconsidered.
At the core of this failure lies neither a lack of innovation nor a lack of validation, but the persistent absence of open, public, data-driven scientific comparisons between competing solutions. In particular, the 3D-Flow processor architecture—formally recognized as a breakthrough in 1993 and never scientifically refuted since—has been systematically excluded from transparent evaluation despite orders-of-magnitude advantages in performance, scalability, and cost.
The consequences extend far beyond high-energy physics.
The fundamental challenge faced by CERN—extracting rare, meaningful signals from overwhelming background radiation in real time—is the same challenge that defines modern medical imaging. Advances in particle-physics trigger systems directly enable advances in early disease detection, where identifying minimal abnormal biological processes can determine whether a disease is cured at an early stage before it becomes fatal. Delays in adopting superior signal-processing architectures therefore translate not only into financial waste, but into lost opportunities to save lives.
Ethical Responsibility of Experts Entrusted with Public Trust
A special responsibility rests with scientists who hold recognized positions of expertise and authority in this field. These experts are routinely entrusted by parliamentarians, funding agencies, and public administrators—many of whom are not technical specialists—to provide honest, independent, and competent scientific judgment in decisions involving vast public resources.
This responsibility is not passive. Scientists with integrity have an affirmative duty to demand full transparency and a mandatory, public, technical audit whenever competing technologies show orders-of-magnitude differences in performance, scalability, and cost. Silence in the face of such disparities does not constitute neutrality; it constitutes abdication of professional responsibility.
When experts are presented with a technology that demonstrates substantial, quantified advantages, and when those advantages remain unrefuted after decades of scrutiny, scientific integrity requires more than informal discussion or private skepticism.
If, after rigorous and good-faith analysis, an expert cannot produce quantitative, reproducible arguments that substantially invalidate the demonstrated superiority and societal benefits of the 3D-Flow architecture and its medical derivative, 3D-CBS, then continued neutrality becomes ethically indefensible.
In such circumstances, scientific honesty and responsibility to the public require one of two actions:
- To publicly and technically refute the claims with documented evidence; or
- To formally acknowledge that the technology merits public funding directed to the inventor in order to enable experimental validation of the invention.
Silence, delay, or informal appropriation without acknowledgment misleads non-expert decision-makers, perpetuates waste, and delays technologies with profound societal impact.
Invitation to Formal Endorsement Based on Scientific Integrity
Accordingly, qualified experts who, after examination, find no substantial scientific basis to dismiss the demonstrated superiority and cost-effectiveness of the 3D-Flow and 3D-CBS technologies are explicitly invited—and ethically encouraged—to state this conclusion in writing.
Such letters of endorsement are not acts of personal allegiance. They are instruments of transparency, intended to inform funding agencies and public officials—who must rely on expert guidance—that experimental verification is scientifically justified and ethically necessary.
Similar endorsements have already been provided by respected scientists and technology leaders, including the inventor of the pocket calculator, former CERN Division and Group Leaders, and senior researchers from academia and industry. These statements are publicly available at:
https://crosettofoundation.org/testimonials/
Their purpose is simple: to ensure that decisions affecting billions in public funds and millions of human lives are made on the basis of evidence rather than institutional inertia or unsubstantiated opinions.
Institutional Obligation and Final Call
Parliamentarians and public administrators entrusted with taxpayer resources are not required to resolve technical disputes. They are, however, obligated to demand transparency, public procedures, and measurable accountability. Closed-door evaluations, anonymous rejections, and the absence of public technical comparisons are incompatible with democratic governance when the stakes are this high.
The only legitimate path forward is the organization of public, adversarial scientific reviews—in both particle physics and medical imaging—where competing technologies are compared openly using quantified metrics, and where conclusions and decisions are fully documented and disclosed.
This is not a conflict between individuals or institutions. It is a test of whether science serves truth, humanity, and the public interest.
History will judge this moment not by intentions, but by actions taken when the evidence was already available.
Please Donate to the Crosetto Foundation to support Transparency in Science
Help us build two 3D-CBS prototypes and carry out an experimental trial to demonstrate that we can cut premature cancer deaths and related costs in half.
Donate online: https://crosettofoundation.org/donate-now/
Donate via Zelle: donate@crosettofoundation.org
The Crosetto Foundation has received GuideStar’s Gold Seal for Transparency for 8 consecutive years.
Why Your Donation Matters
Your contribution empowers transparency in science and supports the acceleration of life-saving innovations.
A donation is not just financial support—it is the driving force that enables broader PR campaigns, reaching more journalists, parliamentarians, and citizens who deserve the truth.
Without donations, this vital message [7] risks being silenced. With your support, we can expand awareness through more media outlets—many of which have already exposed harmful scientific inconsistencies (see the partial list of the outlets that have published it [5])—making these issues impossible to ignore and thereby help save lives.
Please consider making a donation today—because the truth must be heard, and together we can ensure it reaches the world.
Spread the Word
- Share this information with your networks.
- Forward it to scientists, journalists, policymakers, and advocacy groups.
- Use social media to call for a public, evidence-based comparison of CERN’s and Crosetto’s technologies.
Write to your representative:
In United States:
In Europe:
A template letter addressed ‘To Whom It May Concern’ is downloadable here [63]. Send it to your representative and/or to the person listed above who holds a position of responsibility for advancements in science for the benefit of humanity and who is committed to eradicate cancer. Send also a copy of your letter to jcolburn@crosettofoundation.org, so that the Foundation can forward it to relevant funding agencies and record your support for transparency in science.
Contact
Jennifer Colburn
Crosetto Foundation for the Reduction of Cancer Deaths
DeSoto, Texas
jcolburn@crosettofoundation.org
https://crosettofoundation.org/
Blog: https://crosettofoundation.org/blog/
Facebook: https://www.facebook.com/profile.php?id=100064846172129
Instagram: https://www.instagram.com/dariocrosetto/
Linkedin: https://www.linkedin.com/in/dario-crosetto-4b69a1227/
X: https://x.com/crosettodario
Puoi supportare la Trasparenza nella Scienza con una Donazione alla Crosetto Foundation.
Per donazioni dall’Italia:
- Banca: CRS – Cassa di Risparmio di Savigliano
- Conto intestato a: Associazione Fondazione Crosetto – ODV – ONLUS
- IBAN: IT53E063054640000050129593
- BIC: SARCIT2S
- Puoi contribuire con il 5 per mille indicando il Codice Fiscale: 962079895.
Ogni piccolo contributo ci permette di informare i politici e gli amministratori dei fondi pubblici e accelerare i finanziamenti per invenzioni che rivoluzionano la scienza. Aiutaci a risparmiare miliardi di fondi pubblici e a costruire dispositivi in grado di dimezzare le morti per cancro e i costi relativi alla Sanità.
Callouts:
- “History judges science by actions taken when evidence was already available”
- “Scientific integrity requires refutation or endorsement—not delay, silence, or copying”
- “Transparency in science is not optional when public money and lives are at stake”
- “Your Taxes, Their Silence: Why is CERN avoiding a head-to-head comparison? Demand fiscal responsibility in global science”
- “Stop the Waste: Over $4B in public funds spent on inefficient tech at CERN. Demand a transparent, public technical review now”
- “The 3D-Flow Challenge: A breakthrough architecture recognized in 1993. Why hasn’t it been openly compared to FPGAs at CERN?”
- “From Physics to Healing: The same tech used to find particles can find cancer early. Why is this life-saving leap being suppressed?”
- “Detect Cancer Sooner: 98% survival for early-stage breast cancer. We have the tech to find it. We need to fund the inventor to build it.”
- “No favoritism on $6B to eradicate cancer, demand Nelson organize a public meeting between inventor Crosetto and CPRIT and let science truth emerge”
- “Your contribution empowers transparency in science and supports the acceleration of life-saving innovations”
Additional References:
____________________________
[1] Donate: Support the Crosetto Foundation online (https://crosettofoundation.org/donate-now/) or if you have Zelle app on your phone or computer, send your donation directly to donate@crosettofoundation.org.
[2] 04/14/2025. Crosetto’s scientific article, title ‘3D-FLOW OPRA for Level-1 Trigger: A Breakthrough Invention Capable of Extracting ALL Valuable Information from Radiation, Providing a Very Powerful Tool to Discover New Particles, Reduce HEP Costs, Advance Science and Benefit Humanity’ documents and details the content of his 2-hour, 102-slide presentation delivered at the IEEE-NSS-MIC-RTSD conference in Tampa, Florida on 31 October 2024 (https://bit.ly/4oNUOyT), (https://drive.google.com/file/d/1JyAw9Ba9DWRjlKwsSoz8j4KEPGDoiDwR/view?usp=sharing).
[3] 08/28/2025, Press Release English title: ‘Urgent Appeal: Freeze CERN Funding, Fund Innovations Suppressed for 32 Years That Can Save Millions of Lives and Billions of Euros’ which describes the missed opportunities that result in the loss of billions of taxpayer euros and millions of lives, in HTML: https://bit.ly/4p0DneC, in PDF: https://bit.ly/3UCW8XE.
[4] Budget and Waste Analysis: An evaluation of CERN’s cost ranges, daily operating expenditures, and estimated spending for the LHC and HL-LHC. (https://bit.ly/45XONYW), (https://drive.google.com/file/d/1vhlFDBXukvzZIAq93JRohgOOwCAv595x/view?usp=sharing).
[5] 11/10/2025, Links to the Press Releases published by over 5,000 NEWS Outlets (https://bit.ly/3HtisQv) that have reached a potential of over 800 million readers.
[6] 11/07/2025 Press Release English title: ‘Call for Scientific Integrity at CERN: More than $4 billion in taxpayer funds have already been wasted, and over $12 billion more is set to be wasted over the next decade as transparency is suppressed’ HTML: https://bit.ly/43idsFY.
[7] 10/28/2025. Press Release, English, title: ‘Evidence Against Evidence: CERN-IEEE FPGA vs. Crosetto 3D-Flow, a Breakthrough Invention Recognized 32 Years Ago That Could Have, and Can Still, Save Billions of Euros and Millions of Lives’, HTML: https://bit.ly/4qKVar8. in PDF (https://bit.ly/3UCW8XE), (https://drive.google.com/file/d/1ixCMjupsJIDdAhe7-RFIKiKtuKEVqqM1/view?usp=sharing).
[8] 09/15/2025. Press Release, English, title: ‘Request for Secretary of State of Texas, Jane Nelson, to Organize a Public Meeting Between Crosetto and CPRIT Scientists Who Have Allocated $3.65 Billion of $6 Billion to Cancer Research’. HTML: https://bit.ly/41TMUKF.
[9] 09/06/2025. Press Release, English, title: ‘CERN’s FPGA Failure and the Suppression of 3D-Flow and 3D-CBS: A Call to Save Millions of Lives and Billions of Euros’. HTML: https://bit.ly/3HYBePY.
[10] 07/15/2025. Press Release, English, Title: ‘Urgent Appeal: Freeze CERN Funding—Fund Innovations That Can Save Billions and Millions of Lives’. HTML: https://bit.ly/4m57FKZ.
[11] 07/04/2025. Press Release, French, Title: ‘Seule la transparence et la responsabilité peuvent sauver le CERN : une condition essentielle pour mettre fin au gaspillage de milliards et accélérer les innovations médicales vitales’. HTML: https://bit.ly/4lfjnTe.
[12] 07/04/2025. Press Release, German, Title: ‘Nur Transparenz und Rechenschaftspflicht können das CERN retten: Milliardenverschwendung stoppen, lebensrettende Innovationen ermöglichen’. HTML: https://bit.ly/3TTV0yb.
[13] 07/04/2025. Press Release, Italian, title: ‘Solo la Trasparenza e la Responsabilità Possono Salvare il CERN: una Condizione Essenziale per Porre Fine allo Spreco di Miliardi e Accelerare le Innovazioni che Salvano la Vita’. PDF: https://bit.ly/4loi7go.
[14] 07/03/2025. Press Release, English, title: ‘Only Transparency and Accountability Can Save CERN: Stop Billions in Waste, Unlock Life-Saving Innovations’. HTML: https://bit.ly/44cIbVQ.
[15] 06/30/2025. Press Release English, title: ‘Only Transparency and Accountability Can Save CERN: Looming Crisis, Billions Wasted, Science Stalled, Innovations Blocked from Reaching Cancer Patients’. HTML: https://bit.ly/3TMnDNI
[16] 06/23/2025. Press Release, English, title: ‘Respectful Request to Submit a Parliamentary Question on CERN’s Transparency and Accountability to prevent further Waste of EU Funds’. PDF: https://bit.ly/4era28b.
[17] 06/23/2025. Press Release, Italian, title: ‘Richiesta Rispettosa di Presentare un’Interrogazione Parlamentare sulla Trasparenza e Responsabilità del CERN per Prevenire Ulteriori Sprechi di Fondi UE’. PDF: https://bit.ly/3T7G1R8
[18] Crosetto DB. The 3D-Flow architecture explained in one page https://bit.ly/4hbX8fl
[19] The official report from the Fermilab public scientific review on December 14, 1993. The committee recognized the 3D-Flow invention as a breakthrough that allows a programmable Level-2 pattern recognition algorithm to be executed at Level-1 on datasets arriving every 25 nanoseconds without data loss. The report affirmed the invention’s feasibility and found no major flaws. (https://bit.ly/41i4ace), (https://drive.google.com/file/d/0BxWfo2ViJ6r5amx4ZlN2OTJqMmM/view?usp=sharing&resourcekey=0-oYLJQocSy9BOTGb68vsu9A)
[20] The U.S. Department of Energy (DOE) awarded a $1 million grant to Crosetto to conduct a feasibility study of his 3D-Flow invention (https://bit.ly/3Pszu1y), (https://drive.google.com/file/d/0BxWfo2ViJ6r5anZtOG1rY250dEk/view?usp=sharing&resourcekey=0-GhQN7cqFP2z7kI9XLfrRlQ).
[21] Crosetto, Peer-reviewed 45-page article published on Nuclear Instruments and Methods in Physics Research Sec. A, vol. 436, (1999) pp.341-385. The article is reporting the successful results of the feasibility study from system level to gate and transistor level of Crosetto’s 3D-Flow Architecture that he performed with a $1 million grant received from DOE. (https://bit.ly/45Mw6pM), (https://drive.google.com/file/d/0BxWfo2ViJ6r5NlVSWHhoTl9jZXc/view?usp=sharing&resourcekey=0-NPvfp2wWcJrD0ins-cx4Cw)
[22] Crosetto, DB.: ‘A modular VME or IBM PC based data acquisition system for multi-modality PET/CT scanners of different sizes and detector types.’ Presented at the IEEE Nuclear Science Symposium and Medical Imaging Conference, Lyon, France, 2000, IEEE-2000-563. Short URL (https://bit.ly/3JRlRZZ), (https://drive.google.com/file/d/0BxWfo2ViJ6r5MTBoTVRucF9CREU/view?usp=sharing&resourcekey=0-2ofmkGvM39MMc-R3A8mQjw).
[23] Crosetto, DB.: ‘Real-time, programmable, digital signal-processing electronics for extracting the information from a detector module for multi-modality PET/SPECT/CT scanners.’ Presented at the IEEE Nuclear Science Symposium and Medical Imaging Conference, Lyon, France, 2000, IEEE-2000-567. Short URL ( https://bit.ly/4fZTzZC), Full URL (https://drive.google.com/file/d/0BxWfo2ViJ6r5d1NENTRkSUg2NVU/view?usp=sharing&resourcekey=0-HBFHiHO9nHghdaEHxZoaDQ)
[24] Crosetto DB: ‘400+ time improved PET efficiency for lower-dose radiation, lower cost cancer screening.’ Technical-scientific book of Crosetto’s 3D-CBS (3D Complete Body Screening) invention, presented and distribute 200 copies free-of-charge at the IEEE Nuclear Science Symposium. and Medical Imaging Conference., Lyon, France, 2000: ISBN 0-9702897-0-7. Included in 2000 in the U.S. Library of Congress Catalog-in-Publication Data Card Number: 00-191510A (https://bit.ly/45U2Wqv), ISBN 0-9702897-0-7, (https://drive.google.com/file/d/0BxWfo2ViJ6r5WVFVWnJteENqMWc/view?usp=sharing).
[25] 2001 (First Proof): Crosetto presented a working hardware proof of concept at the IEEE-NSS-MIC conference in San Diego, (CA) (https://bit.ly/4oG9pLG) (https://drive.google.com/file/d/0BxWfo2ViJ6r5anppNndvTmkxWGM/view?usp=sharing&resourcekey=0-G9NU2S2ySj6MqKPAbPO-5g).
[26] Crosetto’s schematics and PCB layouts of the 3D-Flow electronics board he designed and built in 2003, which have a 10 picosecond resolution and a 40 picosecond maximum skew across thousands of boards in many crates. (https://bit.ly/4l64nWP), (https://drive.google.com/file/d/0BxWfo2ViJ6r5Wl82SG0xSC1hakU/view?usp=sharing&resourcekey=0-pd-KaM-vdJmBKgVzHXsRDA).
[27] Crosetto DB article ‘The 3-D Complete Body Screening (3D-CBS) Features and Implementation’ Conf. Rec. IEEE-NSS-MIC, Portland, Oregon, IEEE 2003-M7-129. (https://bit.ly/43Rlk0s), (https://drive.google.com/file/d/0BxWfo2ViJ6r5RDQ2UURPeHBIYnc/view?usp=sharing&resourcekey=0-6MP6-KUT13Y2b8rSCqFtjQ),
[28] CERN-CMS FPGA-Based Level-1 Trigger was dismissed in February 2016 because it was ineffective as stated in the second paragraph of the introduction of the article: ‘The legacy Level-1 trigger system is composed of approximately 4000 data processor boards’ by scientist of the same CMS Collaboration (https://cds.cern.ch/record/2194548/files/CR2016_121.pdf).
[29] A 274-page proposal by Crosetto DB. detailing the 3D-Flow OPRA and 3D-CBS projects. The proposal was submitted to the U.S. Department of Energy on 22 December 2015, after Crosetto was solicited by the Director of the Office of High Energy Physics of the Office of Science of DOE, to design a universal programmable Level-1 Trigger that would meet the requirements of all LHC experiments. (https://bit.ly/4myTwpY) (https://drive.google.com/file/d/0BxWfo2ViJ6r5MlpkbUpjbEIybUk/view?usp=sharing&resourcekey=0-8RpD1TC0IGKAEZ9L5-DrJw )
[30] The 378-page CERN official document, CERN-CMS-TDR-022, titled ‘The Phase-2 Upgrade of the CMS Data Acquisition and High-level Trigger Technical Design Report,’ dated 17 June 2021, on page 46, Table 3.2. list 130 ATCA crates (5kW/crate = 650 kW), 1226 boards, 1,648 FPGAs totaling >20 trillion transistors (https://cds.cern.ch/record/2759072/files/CMS-TDR-022.pdf)
[31] References to CERN-ATLAS and CMS Level-1 Trigger TDR detailing their trigger boards and calculation of the 20 trillion transistors on pages 70 to 73 of (https://bit.ly/4e1uURA) (https://drive.google.com/file/d/1JyAw9Ba9DWRjlKwsSoz8j4KEPGDoiDwR/view?usp=sharing ).
[32] A slide presented at the CERN auditorium on 21 May 2019, describing the WPET (Wearable PET) project. This project, which received funding from the CERN-ATTRACT Consortium and utilized EU taxpayer money, involves an impractical, absurd 350+ kg coat intended for 24-hour cancer screening. (http://bit.ly/2JWsxG2), (https://drive.google.com/file/d/1-CWKfAWi5sTOD2USvVFQOYie_6d-1IdT/view?usp=sharing)
[33] Crosetto DB., provided a paragraph-by-paragraph refutation of the article requesting funding for the €2 million WPET-Jacket project, but he never received a feedback for his review. (https://bit.ly/3iydDp3), (https://drive.google.com/file/d/1mHoX59_lklPHj95JCCpVPLUlsUYFDwjj/view?usp=sharing)
[34] A parliamentary question submitted to the European Parliament on 21 June 2019, by the Honorable Alessandro Panza. The question demanded accountability from CERN regarding its decision to fund the WPET project for cancer screening instead of the 3D-CBS project. (https://bit.ly/3HKjreL), (https://drive.google.com/file/d/1XwNqFk_2XU7Mjvw0tPFBtkzuiaX1g8jL/view?usp=sharing ), (https://www.europarl.europa.eu/doceo/document/E-9-2021-003244_EN.html).
[35] An educational video showing the bypass switch/register analogy to illustrate the conceptual invention of the 3D-Flow architecture at minute 4:28 (https://bit.ly/4oN7Xbx), (https://www.youtube.com/watch?v=HwMnHRuWo4o).
[36] Instead of stopping funding CERN-ATTRACT and requesting CERN accountability by organize a public meeting between the author of the WPET and 3D-CBS for cancer screening, the European Commission awarded an additional €28 million grant to the CERN-ATTRACT program https://cerneu.web.cern.ch/attract-unveils-projects-will-benefit-its-eu28-million-fund-innovation
[37] Crosetto DB., A 102-slide, 2-hour presentation by Crosetto at the IEEE-NSS-RTSD conference on October 31, 2024. The presentation compares the ATLAS/CMS 1992 logic and the 3D-Flow paradigm, including operational examples (https://bit.ly/45uaZtz), (https://drive.google.com/file/d/1X82XVQbOgHjeHF8OpkIJo-Cfz8AuhMec/view?usp=sharing).
[38] Crosetto DB. A two-page technical comparison of performance, power consumption, and costs of the 3D-Flow versus the FPGA Level-1 Trigger systems, submitted to the 2025 IEEE-NSS-MIC-RTSD conference in Yokohama, Japan. (https://bit.ly/45K6BFz) (https://drive.google.com/file/d/1BLB6z0r3W-RYl4jVgv0k8Kdtqs-kz99x/view?usp=sharing)
[39] Crosetto DB., A two-page brief about the modular universal, scalable 3D-Flow board for Level-1 Trigger, detailing its form factors and applications in physics and PET applications, submitted to the 2025 IEEE-NSS-MIC-RTSD conference in Yokohama, Japan. (https://bit.ly/41hKwgk), (https://drive.google.com/file/d/1Ceb2NWaY9TU4_-oGa1olB5VG00r7mLSI/view?usp=sharing).
[40] 20 June 2025 CERN Council approved the Medium-Term Plan for 2026–2030 for Phase 2 upgrades of ATLAS and CMS (https://bit.ly/4oIjSWV) (https://home.cern/news/opinion/cern/news-june-2025-cern-council-session), (https://drive.google.com/file/d/1aTIvwi9ovdZW_RypQLgo3qsAMUYcFrt2/view?usp=sharing).
[41] 16 July 2025. Letter from Crosetto DB., to 43 IEEE and world leaders explaining the importance of his two papers submitted to the 2025 IEEE-NSS-MIC-RTSD conference and requesting a ‘Feedback’ (https://bit.ly/4m57FKZ), (https://drive.google.com/file/d/1gj0tuWBtJcElYAQY_g-1NJ2R51Zk2IPY/view?usp=sharing).
[42] 29 October 2025 Letter from Crosetto to IEEE organizers and leaders in the field and laws enforcement requesting permission to distribute scientific information (https://bit.ly/4awnSGj), (https://drive.google.com/file/d/1HoT6VGPwj1mN8H9WR2tOc4S99VJygV8R/view?usp=sharing).
[43] 3 November 2025. Video of the Plenary Session showing NSS Chair preventing Crosetto from asking a question to the keynote speaker (https://youtu.be/24pr4jRmwcM).
[44] 14 November 2025. Formal request directed to CERN CMS and ATLAS leaders and trigger experts, demanding a response to two critical questions regarding the FPGA-Based Level-1 Triggers built for the 2026–2036 High-Luminosity LHC (HL-LHC) experiments (https://bit.ly/4aBElsN), (https://drive.google.com/file/d/1E7K2oEESYwd-kHfvDjaq8rXvQg4w_0Ep/view?usp=sharing).
[45] 7 November 2025. Slide presented at the IEEE-NSS closing session showing the List of 2025 NSS Topics (https://bit.ly/4pXfT9W), (https://drive.google.com/file/d/1E6IxXSs7oyD4d113GJlEtg_TF5_ZL3Y_/view?usp=sharing)
[46] 7 November 2025. Slide presented at the IEEE-NSS closing session showing the papers rejected at the 2025 IEEE-NSS (https://bit.ly/49XANRz), (https://drive.google.com/file/d/1uV7KI5d06NwaGjYtOf00IrBprevEeiU7/view?usp=sharing)
[47] 7 November 2025. Slide presented at the IEEE-NSS closing session showing the 2026 NSS Topics that removed ‘Trigger’ (https://bit.ly/3MlZs8y) (https://drive.google.com/file/d/1k_VPJBxAp-R3ytZwltGR0_4CwSsu-PxH/view?usp=sharing)
[48] Crosetto DB. Testimonials of his commitment to make the scientific truth emerge for the benefit of humanity (https://bit.ly/4pCXXl2), (https://drive.google.com/file/d/1K57K_jpUnOVR507vmnt8DdDaNedu-jBQ/view?usp=sharing)
[49] 1 July 2003. Report of the public, international scientific reviews of the 3D-CBS innovative technology in Dallas, Texas. The review panel included the inventor of the pocket calculator, Jerry Merryman. See full report at the Short URL https://bit.ly/3i9xCJ9 Full URL https://drive.google.com/file/d/0BxWfo2ViJ6r5eEd4UVlJeU1PX0k/view?usp=sharing.
[50] Crosetto DB. Figure 7 – The entire Level-1 programmable system of over 68,000 x 3D-Flow processors at $0.5 each can fit into a single crate. A patch panel PRAI-ATCA receives events from the detectors, synchronizes and formats each event into 4,096 channels datasets and send them to the 3D-Flow system —one every 25 nanoseconds. (https://bit.ly/4q96k7E), (https://drive.google.com/file/d/1ZL6czut0U7JO4T2DZIYTW2ZnIU5o-g4n/view?usp=sharing).
[51] Crosetto DB. Figure 8 – Overview of the crates of the 4,096 channels complete 3D-Flow-Based Level-1 Trigger system suitable for multiple experiments (https://bit.ly/3M2IpIs), (https://drive.google.com/file/d/1nsA9ItlOlkpUvaMWmmnU7TcvNIr1I8bC/view?usp=sharing).
[52] Crosetto DB., Figures 9 and 10. View of the component layout on a 512-channel VXI board with 66 ICs (8,448 x 3D-Flow PEs). (Available in PDF at: https://bit.ly/48Ufk9J), (https://drive.google.com/file/d/155wjkq3PeVzdbtvCYBM6BLkiohpBKVve/view?usp=sharing).
[53] Crosetto DB. ‘3D-CBS: The first true paradigm change in biomedical imaging invented 20 years ago, confirmed by measured results as able to provide a safe, very early, lifesaving cancer detection…’ A 147-page article on the 3D-CBS technology for measuring bio-physiology. The article was submitted on 6 July 2020 to the Journal of Medical Imaging (JMI) along with a request for JMI to withdraw a previous article by other authors that Crosetto claims was misleading researchers. The Journal of Medical Imaging excluded Crosetto’s article from review without providing a scientific reason and did not withdraw the other article (http://bit.ly/2QdgdTx), (https://drive.google.com/file/d/1jcMBP43bPooy9t94ZxRdHOkFtaN6zsXZ/view?usp=sharing)
[54] Crosetto DB. A roadmap table and supporting data estimating the lives saved and projected revenues over 30 years from using the 3D-CBS device for early cancer detection. (https://bit.ly/47eqiIh), (https://drive.google.com/file/d/1qYC3vzGm2CO37ZVsCUM05Op4Je_zz_GF/view?usp=sharing).
[55] Crosetto DB. Figure 11 – Logical and physical layout of the 3D-Flow 6U-VME Crate Configuration: PEs, Connectors and Cables for 2,304 Channels (>2,000 Ops/Dataset), Designed for Cost-Effectively Measuring Photon Energy, Time, and Resolution from Low-Cost Crystal Detectors in High-Sensitivity 3D-CBS (Available in PDF at: https://bit.ly/48Qthpf), (https://drive.google.com/file/d/1iFUYKjV5XoNiTuNBRRbDrw88CTsxVVRe/view?usp=sharing).
[56] Crosetto DB. Figure 12. Component layout on a 128-channel 6U-VME board with 12 ICs (1,536 x 3D-Flow PEs). (Available in PDF at: https://bit.ly/44t3Mcl), (https://drive.google.com/file/d/19XqMuBLsmFf04vqzaavjZdXgqyci0aUV/view?usp=sharing).
[57] 9 December 2025. CERN article also published on CERN website stating ‘Fifty million billion particle collisions…’ https://bit.ly/4qjwV2h. (https://drive.google.com/file/d/1MC2EziuyazvHyzrKw6_CkR9LDy2G_pkA/view?usp=sharing
[58] Texas Secretary of State Jane Nelson’s video stating her commitment to eradicate cancer with a €6 billion bill for Cancer Research (https://bit.ly/4e7QVPp), (https://www.youtube.com/watch?v=v7VJhz7easo).
[59] Crosetto DB., designed and built the Fast Digital Parallel Processing module FDPP (https://bit.ly/2CX6CfY) modular electronic boards which implemented a parallel-processing architecture suitable for maintaining the focus of the beam of the Super Proton Synchrotron accelerator at CERN. These boards also provided physicists with a powerful tool for executing a programmable Level-2 Trigger to detect unknown particles (https://bit.ly/4s1bkwV), (https://drive.google.com/file/d/0BxWfo2ViJ6r5cTl0OXZYTjVGeFU/view?usp=sharing&resourcekey=0-xauS3e0j985iigcaoFrtLw).
[60] United States Representatives contacts: Write to your representative in U.S.: https://www.house.gov/representatives/find-your-representative
[61] European States Parliamentarians contacts: Write to your national parliamentarians of all European states: https://secure.ipex.eu/IPEXL-WEB/parliaments/list_parliaments
[62] European Parliamentarians contacts: Write to the 720 members of the European Parliament. https://www.europarl.europa.eu/meps/en/full-list/all
[63] Template letter to assist you in drafting a message to your representative. (https://bit.ly/4j4J74s), (https://drive.google.com/file/d/1zSgLZin69ZaSFcuzc_HjITkbQ8iTe1Pa/view?usp=sharing)
